According to the recent development of technology, a digital phase-locked loop (ADPLL) has been widely used instead of a charge-pump phase-locked loop (CPPLL) having a problem of an analog circuit.
A time-to-digital converter is a significant configuration in the digital phase-locked loop performing the same function as that of a phase-frequency detector (PFD) in the charge-pump phase-locked loop in the related art.
However, the time-to-digital converter, for example, a delay-line based TDC, a stochastic TDC, a time-amplifying TDC, and a ring-oscillator based TDC, of the related art is operated only as a phase-detector (PD) in terms of a narrow operation range.
The phase-detector (PD) may be operated only when a difference between two frequencies is very small, and in a case where a loop band range is decreased in order to decrease jitter, there is a problem in that an operation range of the phase-detector is also decreased.
Recently, researches for expanding an operation range of the time-to-digital converter have currently been conducted.